1. Field of the Invention
This invention relates to integrated circuit testing. More particularly, this invention relates to integrated circuit testing using serial scan chains for applying signals to and capturing signals from predetermined nodes within an integrated circuit.
2. Description of the Prior Art
Integrated circuit testing using serial scan chains is known from the JTAG system that is the subject of IEEE Standard 1149.1-1990. In accordance with this Standard, an entire integrated circuit is treated as a whole and tested together. With the increasing complexity of integrated circuits, this has the result that the total number of nodes at which it is desired to sample and apply signal values increases making the serial scan chains longer. Lengthening of the serial scan chains has the result that a greater time is needed to shift in the data to fill the scan chain in order to apply signals to a particular set of nodes, which may be positioned in the middle or towards the end of the scan chain. Similarly, a greater time is needed to shift out particular captured data.